Design of Optimized Bit Parallel Multiplier Based 32-Point Mixed R2SDF-R4MDC FFT Architecture

We present a novel pipelined Fast Fourier Transform (FFT) architecture which is capable of producing the output sequence in normal order. The Fast Fourier Transform (FFT) is periodically employed in the algorithms of signal processing for the applications of Orthogonal Frequency Division Multiplexing (OFDM). In this paper, a new pipelined 32 point Mixed Single-path Delay FeedbackMulti-path Delay Commutator (SDF-MDC) FFT architecture is designed for performing the frequency transformation techniques. Delay Feedback (DF) and Delay Commutator (DC) based structures are traditionally used to optimize the FFT architecture. A new architecture called “32-point Mixed R2SDF-R4MDC” FFT structure is proposed in this paper is to calculate the frequency representation of discrete time input sampled signals. The pipelined 32-point Mixed SDF-MDC FFT architecture is used to increase the speed of processing element. In addition, the structure of Bit Parallel Multiplication (BPM) has been changed to improve the performance of twiddle factor multiplier of FFT architecture. Optimized BPM structure has used only little hardware to perform the twiddle factor multiplication. Finally, optimized BPM structures have been integrated into R2SDF-R4MDC FFT structure for alleviating the performances of frequency transformation process.This architecture is applied for 32point FFT and compared to Single-path Delay Feedback and Multi-path delay Commutator in terms of throughput, latency and hardware complexity. The performance evaluation of proposed architecture is determined through Very Large Scale Integration (VLSI) system design environment. Less area utilization, low power consumption and high speed are the main concerns in VLSI system design environment. Hence, the aim of new proposed architecture is used to reduce the hardware complexity, power consumption and also increase the speed and throughput of the system. Proposed new pipelined 16-point Mixed SDF-MDC architecture offers 9.07% reduction of Slices, 11.4% reduction of LUT’s, 6.07% reduction of Latency than the existing method.